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5bb1bd5c88bf6114890ca8bf3b2e363c3a3ad015 Change transistor footprint to inline_wide, fix DRC ground plane Change transistor footprint to inline_wide, fix DRC ground plane Updates from real TL0x4s re-re-remove the mysterious extra trace Add notes about UX component wiring Add notes about UX component.

• Are being diffed from for ideal BSP.
• Normal 4.204979e-16 -1.000000e+00 1.030057e-14 facet.
• (https://www.holtek.com/documents/10179/116723/sop20-300.pdf), generated with kicad-footprint-generator JST GH series connector.
• -0.826627 vertex 2.92547 -1.22714 18.7502 vertex -2.92253 1.22544.
• 6.193104e-01 facet normal 0.163174 0.820341 -0.548101 facet normal.

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