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Pitch 0.65mm Slug Down Thermal Vias (PowerSO-20) [JEDEC MO-166] (http://www.st.com/resource/en/datasheet/tda7266d.pdf, www.st.com/resource/en/application_note/cd00003801.pdf HSOP, 32 Pin (https://www.nxp.com/docs/en/package-information/SOT358-1.pdf), generated with kicad-footprint-generator connector Molex Micro-Latch top entry JST SH series connector, BM13B-ZESS-TBT (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator Molex Mini-Fit Jr. Power Connectors, old mpn/engineering number: 5569-14A2, example for new part number: 26-60-5020, 2 Pins per row (http://www.molex.com/pdm_docs/sd/1053101208_sd.pdf), generated with kicad-footprint-generator Molex SPOX Connector System, 53048-0510, 5 Pins per row (http://www.molex.com/pdm_docs/sd/530470610_sd.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py 16-Lead Ultra Thin Quad Flatpack (PH) - 16x16x1 mm Body, 2.00 mm [TQFP] (see Microchip Packaging Specification 00000049CH.pdf SC-74, 6 Pin (https://www.silabs.com/documents/public/data-sheets/si512-13.pdf), generated with kicad-footprint-generator Single banana socket, footprint - 6mm drill Dual banana socket, footprint - 6mm drill Dual banana socket, footprint - 3 x 6mm drills 3 pin Molex header 2.54 mm spacing 3 pin Molex connector 2.54 mm spacing Q1, Q2, Q3, Q4, Q5 R1, R2, R23, R24 | 4 | 100 nF | Unpolarized capacitor | | C6, C7, C8, C9 D1, D2, D3, D4, D5, D8, D9, D10 | 8 "active_layer_preset": "All Layers", "active_layer_preset": "All Layers", "active_layer_preset": "All Layers", "active_layer_preset": "All Layers", "active_layer_preset": "All Copper Layers", re-re-remove the mysterious extra trace re-re-remove the mysterious extra trace f33ea6a168 Add scad for v3.2 Stuff all teh scad files in 2a5bb74bbd0830b4c30d8004e4cdd9ae79e21770 Update Schematics/schematic_bugs_v1.md Clock POT is too small for a clock on the mid surdos, faster than we play it) Paul.

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