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Ird*sin(lf0), h1], [ ord*cos(lf1), ord*sin(lf1), h1], [ 0,0,h2], [ ord*cos(lf0), ord*sin(lf0), h2], [ ord*cos(lf2), ord*sin(lf2), h0], [ ird*cos(lf1), ird*sin(lf1), h2], [ ord*cos(lf2), ord*sin(lf2), h0], [ ird*cos(lf0), ird*sin(lf0), h1], [ ird*cos(lf2), ird*sin(lf2), h1], [ ord*cos(lf1), ord*sin(lf1), h1], [ 0,0,h2], Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) Total plated holes count 16 Not plated through holes: merged pull request 'pcb_finalization' (#1) from pcb_finalization into main 3d279dd88c Finish schematic, add PDF 2d3c489f2a More SR1 notation 2bd01a1ff2d30ca3cff647bbf3b80645437cc07c start e49f4ab127dc081ee1c77dd21e80d128628a1152

Normal -4.942513e-001 -8.649397e-001 8.714973e-002 facet normal 9.987907e-001 1.998141e-003.
In orange. Replacing LEDs in these.
-5.317826e-001 0.000000e+000 vertex 6.917118e+000 -3.993600e+000 0.000000e+000 facet normal.
-9.807886e-01 0.000000e+00 vertex -1.021772e+02 1.042644e+02.

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