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BackBytes Images/retrigger.png | Bin 0 -> 407684 bytes Panels/luther_triangle_vco_quentin_v2.scad | 18 Panels/luther_triangle_vco_quentin_v3.scad | 14 ...ther_triangle_vco_quentin_v3_blank.stl.stl | Bin 0 -> 317907 bytes Images/PXL_20210831_004139245.jpg | Bin 12724 -> 0 bytes From d40f7ca1ca9e3e0f97e1dc4f553b9c659940a311 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Notes from debugging Clock POT is the two clockwise-most pins, looking from below. Clock rate goes down when resistance goes up, opposite to expectation. C1 is too small for a 1uF capacitor. 1uF may be unnecessary.
- 3.44415 3.82299 facet normal 1.401090e-16 -6.187274e-16 -1.000000e+00 facet.
- 8.477229e-01 -3.604418e-03 5.304271e-01 facet normal.
- Put it between rows 5 and 2.
- Inductor 26mm diameter 11mm Fastron.