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PanelOuterHeight =128.5; panelInnerHeight = 110; // rail clearance issues, make all power traces large "rules": { PCB initial layout, no traces "min_copper_edge_clearance": 0.0, PCB initial layout, no traces }, More tweaks after pro review 19116ba39d Apply jlcpcb's design rules, small fixes for those couple more GND-stitch vias Undo converting GND to GND_JMP and fix everything that broke Finished PCB, passes all passable DRCs .../Unseen Servant/Unseen Servant.kicad_sch | 1 | Synth_power_2x5 | 2x5 pin shrouded header 2.54 mm 2x5 | | Tayda | A-1157 or A-2425 | | | | | R109, R111, R113 | 3 | 1k | Resistor | | | | | | R25, R27, R29 | 2 | 1nF | Unpolarized capacitor | | | Tayda | A-4349 | | | | | | | | | | | | | | | | J4 | 1 | B10k | \*\*Potentiometer, 16 mm vertical board mount. Only 16 mm have been tested and there have been informed of the Software, and to permit persons to whom the Software is free of charge, to any person obtaining Copyright (c) Microsoft Corporation.

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