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BackFix some clearance issues, make all power traces large "rules": { PCB initial layout, no traces "copper_text_size_h": 1.5, "copper_text_size_v": 1.5, "copper_text_thickness": 0.3, PCB initial layout, no traces "solder_mask_clearance": 0.0, PCB initial layout, no traces }, More tweaks after pro review "design_settings": { "defaults": { PCB initial layout, no traces "silk_text_size_h": 1.0, "silk_text_size_v": 1.0, PCB initial layout, no traces "copper_text_size_h": 1.5, "copper_text_size_v": 1.5, "copper_text_thickness": 0.3, PCB initial layout, no traces Using the Precision ADSR build notes | C7, C12 | 2 | 10k | Resistor | | | D3, D4, D5, D6, D7, D8, D9, D10 | 8 create mode 100644 Fireball/Fireball.kicad_prl create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Potentiometer_Alpha_RD901F-40-00D_Single_Vertical_CircularHoles_centered.kicad_mod delete mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.kicad_mod create mode 100644 .gitmodules delete mode 100644 Hardware/PCB/precadsr/ao_symbols.dcm create mode 100644 Hardware/PCB/precadsr/ao_symbols.lib delete mode 100644 Hardware/PCB/precadsr/Kosmo_panel.pretty/Kosmo_Panel_Slotted_Mounting_Hole_NPTH.kicad_mod create mode 100644 Hardware/Panel/precadsr-panel/precadsr-panel.kicad_pro.
- HLE-120-02-xx-DV-TE, 20 Pins per row, Mounting: PCB.
- Padvia min_thickness 0.0254) (filled_areas_thickness.