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BackStrip, HLE-149-02-xx-DV-TE, 49 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py PowerPAK 1212-8 Single (https://www.vishay.com/docs/71656/ppak12128.pdf, https://www.vishay.com/docs/72597/72597.pdf Vishay PowerPAK SC70 dual transistor package http://www.vishay.com/docs/70487/70487.pdf powerpak sc70 sc-70 dual Vishay PowerPAK SC70 single transistor package http://www.vishay.com/docs/70486/70486.pdf TO-46-4 with Valox case, based on the footprint. Some options: Bourns PTL series, such as: ** Would need another supplier, mouser sells only in 1000+ for these. Original README: From acf6d57d9f34ce2c424f4c9834d80264fa5ffd89 Mon Sep 17 00:00:00 2001 Subject: [PATCH 2/2] Update README.md * [Schematic](Docs/precadsr.pdf) * PCB layout: front, back How to use for rounding teh top edge. (Other "top rounding *" parameters are only relevant if checked. Enable_top_rounding = false; // Radius of the rail + a safety margin // margins from edges h_margin = hole_dist_side + thickness; working_height = height - v_margin - title_font; saw_out = [output_column, bottom_row, 0]; pwm_duty = [input_column, row_2, 0]; audio_in_2 = [left_col, row_5, 0]; cv_in_2a = [left_col, row_3, 0]; pwm_duty = [width_mm - h_margin - working_width/8, row_3, 0]; manual_2 = [left_col, row_7, 0]; manual_1 = [left_col, row_1, 0]; audio_out_2 = [right_col, row_2, 0]; cv_2b_atten = [right_col, row_1, 0]; fm_in = [h_margin+working_width/8, row_4, 0]; pwm_cv_lvl = [second_col, fourth_row, 0]; triangle_out = [width_mm-h_margin-working_width/4, row_1, 0]; audio_out_2 = [right_col, row_1, 0]; fm_in = [first_col, first_row, 0]; //Second row interface placement f_tune = [second_col, second_row, 0]; //Third row interface placement pwm_in = [first_col, first_row, 0]; c_tune = [width_mm/2, top_row, 0]; f_tune = [h_margin+working_width/8, row_3, 0]; c_tune = [width_mm/2 + h_margin, top_row, 0]; left_rib_x = hole_dist_side + thickness; v_margin = hole_dist_top*2; Potentiometers: - One potentiometer for internal clock signal (possibly external). Commonly called a "Baby 8". 0 0 vertex -5.96308 8.22545 2.19603 vertex 5.96308 -8.22545 2.19603 vertex 9.8813 2.36142 0 facet normal 4.829391e-002 8.571911e-002 9.951482e-001 vertex -5.299474e+000.
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