synth_tools

Back

/551D9466; Reference = P5; ValeurCmp = CONN_1; IdModule = Socket_Arduino_Nano:Socket_Strip_Arduino_1x15; EndCmp BeginCmp TimeStamp = /551D9496; Reference = P1; ValeurCmp = Analog; IdModule = Socket_Arduino_Nano:Socket_Strip_Arduino_1x15; EndCmp BeginCmp TimeStamp = /551D9380; Reference = P5; ValeurCmp = Analog; IdModule = Socket_Arduino_Nano:1pin_Nano; EndCmp BeginCmp TimeStamp = /551D9380; Reference = P6; ValeurCmp = Analog; IdModule = Socket_Arduino_Nano:1pin_Nano; EndCmp BeginCmp TimeStamp = /551D9380; Reference = P3; ValeurCmp = Analog; IdModule = Socket_Arduino_Nano:Socket_Strip_Arduino_1x15; EndCmp BeginCmp TimeStamp = /551D94EF; Reference = P4; ValeurCmp = Analog; IdModule = Socket_Arduino_Nano:Socket_Strip_Arduino_1x15; EndCmp BeginCmp TimeStamp = /551D9414; Reference = P4; ValeurCmp = Digital; IdModule = Socket_Arduino_Nano:1pin_Nano; EndCmp BeginCmp TimeStamp = /551D9496; Reference = P6; ValeurCmp = Digital; IdModule = Socket_Arduino_Nano:1pin_Nano; EndCmp Hardware/PCB/precadsr/precadsr.kicad_pcb Normal file Unescape Hardware/Panel/precadsr-panel/precadsr-panel.pretty/precadsr-panel-art.kicad_mod Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/PPTC_RXEF025.kicad_mod Normal file Unescape "Name": "Top Solder Mask" "Notes": "Type: dielectric layer 1 (from F.Cu to B.Cu)" "Name": "Bottom Solder Paste" "Name": "Bottom Silk Screen" "Name": "Top Solder Mask" "Notes": "Type: dielectric layer 1 (from F.Cu to B.Cu)" "Name": "Bottom Solder Paste" "Name": "Top Solder Paste" "Name": "Top Solder Mask" "Notes": "Type: dielectric layer 1 (from F.Cu to B.Cu)" "Name": "Bottom Solder Paste" "Name": "Bottom Solder Mask" "Name": "Bottom Solder Paste" "Name": "Bottom Solder Mask" "Name": "Bottom Solder Mask" "Name": "Bottom Silk Screen" "Name": "Top Silk Screen" "Name": "Top Solder Paste" "Name": "Bottom Silk Screen" "Name": "Top Solder Mask" "Name": "Bottom Solder Mask" "Notes": "Type: dielectric layer 1 (from F.Cu to B.Cu)" "Name": "Bottom Silk Screen" "Name": "Top Solder Mask" "Notes": "Type: dielectric layer 1 (from F.Cu to B.Cu)" "Name": "Bottom Silk Screen" "Name": "Top Solder Paste" "Name": "Top Silk Screen" Hardware/Panel/precadsr-panel/precadsr-panel-cache.lib Normal file View File Hardware/PCB/precadsr/sym-lib-table Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/PinHeader_1x04_P2.54mm_Vertical.kicad_mod Normal file View File Align panel to integer pseudo-origin, remove testing text, decrease title label font size to 9mm and align it precisely for repeatability d6ebbf1c1b Collect other files not yet included in repo main dd8fda85b1 Update README.md From abc39a50d6580d276015bcd974580f199a987534 Mon Sep 17 00:00:00 2001 Subject: [PATCH] PCB initial layout, no traces PCB initial layout, no traces "min_copper_edge_clearance": 0.0, PCB initial layout, no traces "silk_line_width": 0.15, PCB initial layout, no traces "copper_text_size_h": 1.5, "copper_text_size_v": 1.5, "copper_text_thickness": 0.3, PCB initial layout, no traces Initial kicad, images, gitignore for kicad backups afea9d5a2c Final revision; added custom DRC as project file tstamp 52a45927-621d-4774-9080-e26ba88e3d95) Final revision; added custom DRC as project file tstamp a19ef654-a631-44b9-8b6b-999333495c1b) Final revision; added custom DRC as project file 33729ec97f6dd2ed68c4ca06088ce0b21651948d Align panel to integer pseudo-origin, remove testing text.

New Pull Request

Labels Milestones