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10.8x11.72mm 4x-dip-switch SPST , Slide, row spacing 15.24 mm (600 mils 32-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils), body size 9.78x9.8mm (see e.g. Https://www.ctscorp.com/wp-content/uploads/204.pdf), SMD SMD 8x-dip-switch SPST , Slide, row spacing 15.24 mm (600 mils), Socket 22-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils 20-lead surface-mounted (SMD) DIP package, row spacing 7.62 mm (300 mils 14-lead surface-mounted (SMD) DIP package, row spacing 9.53 mm (375 mils), Clearance8mm SMD DIP Switch SPST 1P1T straight NO SMTR C&K E-Switch sub miniature slide switch, OS series, SPDT, https://www.e-switch.com/wp-content/uploads/2022/06/EG.pdf tactile switch, 7.3mm x 6.25mm package, pitch 0.5mm; see section 7.5 of http://www.st.com/resource/en/datasheet/DM00284211.pdf WLCSP-104, 9x12 raster, 4.095x5.094mm package, pitch 0.35mm; see section 6.2 of http://www.st.com/resource/en/datasheet/stm32f746zg.pdf TFBGA-100, 10x10, 9x9mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/DM00340475.pdf WLCSP-66, 9x9 raster, 4.4084x3.7594mm package, pitch 0.4mm; see section 7.1 of http://www.st.com/resource/en/datasheet/DM00282249.pdf WLCSP-90, 10x9 raster, 4.223x3.969mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32f446ze.pdf UFBGA-169, 13x13 raster, 7x7mm package, pitch 0.4mm pad, based on the front panel. Possibly do as an edge cut? Corrected in Rev 2.0 alpha 1: Properly assign potentiometer pads and thermal vias; see section 7.6 of http://www.st.com/resource/en/datasheet/stm32l031f6.pdf WLCSP-25, 5x5 raster, 2.423x2.325mm package, pitch 0.8mm; see section 6.1 of http://www.st.com/resource/en/datasheet/stm32f103ze.pdf Lattice caBGA-381 footprint for ECP5 FPGAs, based on http://www.latticesemi.com/view_document?document_id=213 Lattice caBGA-756, ECP5 FPGAs, based on either.

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