Labels Milestones
Back6-lead dip package with 1.27mm pin pitch, compatible with SOIC-8, 3.9x4.9mm body, exposed pad, 4x4mm body, pitch 0.5mm, see http://www.ti.com/lit/ds/symlink/tps62177.pdf WSON-10 package 2x3mm body, pitch 0.5mm, thermal vias with large copper area, as proposed in http://www.ti.com/lit/ds/symlink/tps5430.pdf TSOP-I, 24 Pin (JEDEC MO-153 Var BE https://www.jedec.org/document_search?search_api_views_fulltext=MO-153), generated with kicad-footprint-generator Hirose FH12.
- HLE-107-02-xx-DV-PE-LC, 7 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf.
- Href="https://gitea.circuitlocution.com/synth_mages/MK_VCO/commit/56529bef3a0c7d0b31cfccd6b6ce971fb35b4e9c">56529bef3a0c7d0b31cfccd6b6ce971fb35b4e9c Updates from real TL0x4s.
- Out 5e32fb4fc0 Change transistor footprint to inline_wide, fix.