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Plated holes count 16 Not plated through holes: unplated through holes: ============================================================= 0d3d72c49e606725216a5a9a4217e6c039d5a574 c9e81f0cc630cea052574ce7c50b3e82145bb626 Image of caxia score Image of caxia score caixa_sr1.png | Bin 0 -> 292681 bytes rename 3D Printing/{ => Cases}/6u_wing_v1.scad (100% create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/TerminalBlock_dinkle_pluggable_2_P5.00mm.kicad_mod delete mode 100644 Schematics/SynthMages.pretty/P160_pot_hole_nonpcb.kicad_mod create mode 100644 Hardware/PCB/precadsr_Gerbers/precadsr-PTH.drl create mode 100644 Docs/precadsr.pdf create mode 100644 Docs/precadsr_layout_back.pdf (grid_origin 97.28 88.9 Mon 10 May 2021 12:33:34 AM EDT Generated from schematic by Eeschema 5.1.9-73d0e3b20d~88~ubuntu20.04.1 Generated from schematic into main ... Add jlc constraints DRC; replace order number text Compare 19 commits » 2bd01a1ff2 Add schematic, start on PCB Checkpoint after converting most things to SMD 55ee65a5e94ad245f04db09ef472959294e7cca0

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