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### Photos ## Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf) * [BOM](Docs/precadsr_bom.md) * [Build notes](Docs/build.md ``` git clone git@github.com:holmesrichards/precadsr.git New KiCad version; non Al panel Gerbers # Netlist files (exported from Pcbnew *.ses # Exported BOM files *.xml *.csv # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole Total plated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file Unescape DEF Kosmo_panel_Jack_Hole H 0 40 N N 1 F N DEF ao_symbols_Graphic GRAF 0 40 Y N 2 F N DEF SW_Push_Open SW 0 0 Y N 1 F N DEF SW_MEC_5G_LED SW 0 40 Y Y 1 F N DEF SW_Push_Lamp SW 0 0 Y N 1 F N DEF SW_SPDT_MSM SW 0 0 N N 1 F N DEF SW_DP3T SW 0 0 Y N 1 F N DEF 3_pin_Molex_connector J 0 40 N N 1 F N ALIAS SW_E3_SA3624 SW_E3_SA6432 SW_MMI_Q5-100 DEF SW_MEC_5E SW 0 0 PCM_kikit NPTH 0 0 Y N 1 F N DEF SW_Push_Open SW 0 0 Y N 1 F N DEF Synth_power_2x5_passive J 0 40 Y Y 1 F N DEF 3_pin_Molex_connector J 0 40 Y N 2 F N DEF SW_SPDT_MSM SW 0 20 Y N 1 F N DEF SW_SPDT SW 0 40 Y Y 1 F N DEF SW_DIP_x12 SW 0 40 Y N 2 F N DEF SW_DPST_x2 SW 0 40 Y N 1 F N DEF MountingHole H 0 40 N N 1 F N DEF SW_DPDT_x2 SW 0 40 Y N 1 F N DEF SW_MEC_5G_2LED SW 0 0 Y N 1 F N DEF SW_Coded_SH-7040 SW 0 0 PCM_kikit Tab A symbol representing annotation for tab placement Latest commits for file Panels/dual_vca.scad T5 15.200mm 0.5984" (1 hole Total plated.

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