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BackUF tanty looks better than EL\n(higher output, less leakage)\nbut only by a little. 1 µF tantalum.\nYuSynth 1, 10 uF | Polarized capacitor | | | C1, C11, C12 | 2 Hardware/Panel/precadsr-panel/sym-lib-table | 2 ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) Total plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) Total plated holes count 16 ============================================================= Total unplated holes count 0 Minor layout tweaks merged pull request 'Finish schematic, add PDF' (#2) from schematic into main afea9d5a2c Final revision; added custom DRC as project file attr exclude_from_pos_files exclude_from_bom) Final revision; added custom DRC as project file tstamp 30cbcf99-eb70-4e15-8409-33e0ecd46602) Final revision; added custom DRC as project file c4e1c30b9b Add jlc constraints DRC; replace order number text Add jlc constraints DRC; replace order.
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