Update luther's layout Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: merged pull request synth_mages/MK_SEQ#1 Binary files /dev/null and b/SNARE_MANUAL.pdf differ main MK_SEQ/Schematics/Unseen Servant/Unseen Servant.kicad_prl | 2 From 057198b8de00d90dc9311b86f496b649dca09ec0 Mon Sep 17 00:00:00 2001 Subject: [PATCH 15/18] Add jlc constraints DRC; replace order number text Add jlc constraints DRC; replace order number text Fireball/Fireball_panel.kicad_pcb | 3 | 4.7k | Resistor | | | | | | C6, C7, C8, C9 | 4 Docs/precadsr_bom.md | 72 Hardware/PCB/precadsr/potsetc.sch | 4 | 100 nF | Unpolarized capacitor | | | | | | J2 | 1 nF | Unpolarized capacitor | | | | | J3, J4, J5 | 3 | 2_pin_Molex_header | 2 | 47k | Resistor | | | | | | | | D1, D2 | 2 main MK_VCO/Panels/Font files/futura medium condensed bt.ttf | Bin 0 -> 297934 bytes From 8a9583e7df3009c52174c16ce501729b9c90d7ac Mon Sep 17 00:00:00 2001 Subject: [PATCH] Update luther's layout Update luther's layout.
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