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Vertex 4.43928 0.247977 18.7299 vertex 4.32242 0.23878 18.7299 facet normal 0.787396 -0.189041 0.586746 facet normal 0.290168 -0.956976 0 facet normal 0.76849 0.630641 0.108235 facet normal 3.934402e-001 -6.745041e-001 6.246992e-001 vertex 2.795275e+000 -3.166902e+000 2.488700e+001 facet normal -0.462436 0.865129 0.19418 facet normal -1.950737e-01 -9.807885e-01 3.526958e-04 facet normal -0.471435 0.881901 3.73804e-06 facet normal -0.286109 -0.952735 0.102165 facet normal 0.115482 -0.00124902 0.993309 facet normal 2.547723e-01 -7.749087e-04 9.670008e-01 vertex -1.080268e+02 9.665134e+01 8.942076e+00 facet normal 0.768559 0.630556 0.108246 facet normal -1.934024e-01 9.811195e-01 3.622710e-05 vertex -9.619016e+01 1.059942e+02 4.255000e+01 facet normal 0.630682 -0.768461 0.108208 facet normal -0.956942 0.29028 0 facet normal 0.000903236 0.0979891 0.995187 facet normal 4.308032e-01 9.024458e-01 -3.431192e-04 vertex -9.446753e+01 9.232659e+01 2.550000e+00 facet normal 0.598708 -0.491352 0.632552 vertex 7.27387 -4.86024 5.33536 facet normal -0.0977941 0.989287 0.108382 facet normal -0.840149 0.533182 0.0993293 facet normal -0.223445 0.736593 -0.63836 facet normal -5.393305e-002 -9.438277e-002 9.940740e-001 vertex 3.538386e+000 2.819248e+000 2.495526e+001 facet normal 9.613948e-001 4.721924e-003 2.751321e-001 facet normal 5.917222e-02 -3.775003e-03 9.982407e-01 vertex -1.072673e+02 9.695134e+01 8.833620e+00 facet normal 0.119205 -0.00736574 0.992842 vertex -7.75382 1.99084 19.9468 facet normal -0.552477 0.109968 -0.826242 vertex 2.68773 -1.08464 18.9318 facet normal -2.880153e-004 -5.040268e-004 -9.999998e-001 ## Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf ## Git repository https://gitlab.com/rsholmes/precadsr Submodules From 83b013c3637bfb179ad62b90a6c8b2f5fb547c8c Mon Sep 17 00:00:00 2001 Subject: [PATCH] Images, docs updates Images/IMG_6753.JPG | Bin 0 -> 11916 bytes .../Panels/MIRROR IMAGE.png | Bin 0 -> 2506984 bytes Panels/title_test.scad | 22 Hardware/PCB/precadsr/precadsr.sch | 247 (40 Dwgs.User user hide (37 F.SilkS user hide (42 Eco1.User user hide (37 F.SilkS user hide From d48d677c9103ec90137a6830434841a576342e9a Mon Sep 17 00:00:00 2001 Images/capsocket.png | Bin 0 -> 86371 bytes rename LUTHERS_VCO.diy => Schematics/LUTHERS_VCO.diy (100% create mode 100644 Schematics/SynthMages.pretty/C_Rect_L22.0mm_W6.1mm_P20mm_MKT_BIG_RED_CAP.kicad_mod create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/C_Disc_D3.0mm_W1.6mm_P2.50mm.kicad_mod create mode 100644 Hardware/PCB/precadsr_aux_Gerbers/precadsr-F_Paste.gbr create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/PinHeader_1x02_P2.54mm_Vertical.kicad_mod delete mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Potentiometer_Alpha_RD901F-40-00D_Single_Vertical_CircularHoles_centered.kicad_mod create mode 100644 Images/PXL_20210831_002553634.jpg Latest commits for file Panels/title_test_36.stl Latest commits.

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