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]; From 32ece2d681b26731bad50902587b988d6a79e43e Mon Sep 17 00:00:00 2001 Subject: [PATCH] more fixes a5c5ff12ce18fecaaf346f973863d12bf361ac82 Notes from debugging Latest commits for file PCB Notes.txt Normal file Unescape Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756.

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