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BackI mean "shut up". Musescore_example.mscz Normal file Unescape ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole Total plated holes count 16 Not plated through holes are merged with plated holes count 16 ============================================================= Total unplated holes count 0 Minor layout tweaks merged pull request 'pcb_finalization' (#1) from bugfix/10hp into main afea9d5a2cf23e2a33a2927086270d4d602f5a2b 46614f2341 Go to file 74231bd333 Port in fixes from v1.1 007cc05932 Checkpoint after tweaking footprints some more, starting over.
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