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BackDRILL file {KiCad 5.1.10-88a1d61d58~90~ubuntu20.04.1} date Thu Aug 12 11:11:04 2021 ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 Not plated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Fix rail clearance issues, make all power traces large Fireball/Fireball.kicad_pro | 6 Fireball/Fireball.kicad_sch .
- 1-794105-x, 9 Pins (https://www.molex.com/pdm_docs/sd/009652028_sd.pdf), generated with kicad-footprint-generator.
- Normal 0.00125685 0.115521 0.993304 vertex.
- Pacific, 30.48mm diameter vertical toroid mount, 16AWG/1.27mm.
- SIP module, http://www.meanwell.com/webapp/product/search.aspx?prod=nid30 Isolated 1W or 2W Single.