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BackBy { "board": { More tweaks after pro review "clearance": 0.2, "diff_pair_gap": 0.25, "diff_pair_via_gap": 0.25, "diff_pair_width": 0.2, "line_style": 0, "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "Default", "pcb_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.25, "via_diameter": 0.8, "via_drill": 0.4, More tweaks after pro review "clearance": 0.2, "diff_pair_gap": 0.25, "diff_pair_via_gap": 0.25, "diff_pair_width": 0.2, "line_style": 0, "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "Default", "pcb_color": "rgba(0, 0, 0, 0.000)", "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.25, "via_diameter": 0.8, "via_drill": 0.4, More tweaks after pro review }, "pcbnew": { "last_paths": { "gencad": "", "idf": "", "netlist": "", "specctra_dsn": "", "step": "", "vrml": "" }, "schematic": { "annotate_start_num": 0, "drawing": { More tweaks after pro review "extra_units": "error", "global_label_dangling": "warning", "hier_label_mismatch": "error", "label_dangling": "error", "lib_symbol_issues": "warning", More tweaks after pro review 19116ba39d Apply jlcpcb's design rules, small fixes for those 972e45fb78 Go to file f6c7924538 Messing around with panel alignment before printing 9a2ab6dc7f initial notes for v1 front panel components and interconnects between middle and bottom boards. Latest commits for branch.
- Sunlord, SWRB1205S, 12.5x12.5x6.0mm, https://www.sunlordinc.com/Download.aspx?file=L1VwbG9hZEZpbGVzL1BERl9DYXQvMjAyMTA2MTAxMTMyMzc4MTEucGRm&lan=en Inductor.
- Vertex -1.045672e+02 9.927685e+01 1.755000e+01 facet normal -0.630708 -0.768445.