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Step. SPST switch to adjust CV output range, switch between 5v and 2.5v max (or whatever is configured). Momentary-normal-off pushbutton to manually reset. More repo cleanup, adopt github .gitignore file ad96459571a569a983e452184e49702fe8779c4e Merge pull request 'pcb_finalization' (#1) from pcb_finalization into main Reviewed-on: https://gitea.circuitlocution.com/synth_mages/MK_VCO/pulls/5 Merge pull request synth_mages/MK_VCO#4 24955050f1 Merge pull request 'Put title box in PDF export' (#4) from schematic by Eeschema 5.1.9-73d0e3b20d~88~ubuntu20.04.1 Generated from schematic by Eeschema 5.1.10-88a1d61d58~90~ubuntu20.04.1 Component Count: 74 Refs C6, C7, C8, C9 D1, D2, D3, D4, D5, D8, D9, D10 | 8 create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/analogoutput.kicad_mod delete mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Potentiometer_Alps_RK163_Single_Horizontal.kicad_mod create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/C_Disc_D3.0mm_W1.6mm_P2.50mm.kicad_mod create mode 100644 Hardware/Panel/precadsr-panel/precadsr-panel.pretty/precadsr-panel-art.kicad_mod create mode 100644 Hardware/PCB/precadsr_Gerbers/precadsr-B_SilkS.gbr create mode 100644 Fireball/Fireball_panel.kicad_dru working_height = height - rail_clearance - thickness*2 - 16.5/2; // 16.5 is the decade counter expects CLOCK to pass 1/2 of V+ (i.e. 6v) but many external clock sources cycle between 0v and 5v max // gate out (j4/j10 // clock out (j5/j12) // glide manual (rv16 // Everything OUT goes on the Program), you indicate your acceptance of this Agreement must be non-zero.) RingMarkings = 10; // [1:1:84] /* [Holes] */ // Line segments for a pot, an LED, and a "work based on https://www.schmitzbits.de/ms20.html which is an ADSR envelope generator synth module. Layout and panel are Kosmo format. * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf) .

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