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Pot level is used. In loop position, loop\nis connected to trigger, gate jack is normalized\nto +12 V, 10 mA -12 V ## Photos [to be added] ## Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf) * [BOM](Docs/precadsr_bom.md.

Phoenix PT-1,5-7-3.5-H pitch 3.5mm size 35x7.6mm^2.
AR Path="/607ED812/60802B98" Ref="R111" Part="1" AR Path="/607ED812/60802BB2" Ref="R114.
EUS 5 Pin Double.
USB AB receptable, right-angle inverted.

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