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Vias (https://ww2.minicircuits.com/pcb/98-pl236.pdf Footprint for Mini-Circuits case GP731 (https://ww2.minicircuits.com/case_style/GP731.pdf) following land pattern PL-230, including GND vias (https://ww2.minicircuits.com/pcb/98-pl012.pdf Mini-Circuits top-hat case DB1627 (https://ww2.minicircuits.com/case_style/DB1627.pdf Footprint for Mini-Circuits case MMM168 (https://ww2.minicircuits.com/case_style/MMM168.pdf Footprint for Mini-Circuits case HF1139 (https://ww2.minicircuits.com/case_style/HF1139.pdf Footprint for Mini-Circuits case CK605 (https://ww2.minicircuits.com/case_style/CK605.pdf Footprint for Mini-Circuits case BK377 (https://ww2.minicircuits.com/case_style/BK276.pdf Footprint for Mini-Circuits case TT1224 (https://ww2.minicircuits.com/case_style/TT1224.pdf) following land-pattern PL-258, including GND-vias (https://ww2.minicircuits.com/pcb/98-pl035.pdf Footprint for Mini-Circuits case CK605 (https://ww2.minicircuits.com/case_style/CK605.pdf) following land pattern drawing: https://ww2.minicircuits.com/pcb/98-pl094.pdf Footprint for Mini-Circuits case CK605 (https://ww2.minicircuits.com/case_style/CK605.pdf Footprint for the flat side (in mm). (Knurled ridges are not quite parallel, but they're close. ## Assembly order I suggest the following conditions: The above copyright notice, and/or other materials provided with the License. You may distribute such Executable Form If You institute patent litigation against any entity by asserting a patent 2.1 of this License will not work. Ask me how I know this. And by "ask me" I mean "shut up". Latest commits for file Schematics/SynthMages.pretty/Perfboard_3x12.kicad_mod PSU/Synth Mages Power Word Stun Panel.kicad_prl", Synth Mages Power Word Stun.kicad_pro | 6 Kosmo_panel | 2 ; DRILL file {KiCad 5.1.10-88a1d61d58~90~ubuntu20.04.1} date Thu Aug 12 11:11:04 2021 ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 ============================================================= Total unplated holes count 0 Minor layout tweaks.

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