synth_tools

Back

And b/Schematics/bad_trace_v1.jpeg differ Panels/luther_triangle_vco_quentin_v4.scad Normal file View File Panels/title_test_22.stl Normal file Unescape Schematics/SynthMages.pretty/Perfboard_4x12.kicad_mod Normal file View File 3D Printing/Cases/Eurorack Modular Case/EuroRack_Case_26.png Executable file View File Images/PXL_20210831_000949090.jpg Normal file Unescape Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) T5 15.200mm 0.5984" (1 hole T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole Total plated holes count 16 ============================================================= Total unplated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Delete 'Panels/futura medium bt.ttf' From 496e3e33446b55a1a2a83a967e779b5254a33381 Mon Sep 17 00:00:00 2001 Subject: [PATCH 12/13] Update Schematics/schematic_bugs_v1.md Schematics/schematic_bugs_v1.md | 1 | Conn_01x04 | Pin socket, 2.54 mm, 1x4 | | | | | | | | | J9 | 1 | | | | U2 | 1 | ICM7555xP | CMOS General Purpose.

New Pull Request

Labels Milestones