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BackFont size to 9mm and align it precisely for repeatability Change transistor footprint to inline_wide, fix DRC ground plane 5e32fb4fc0953f2a10f8dc9cf7a0a3653bcbf4f2 @circuitlocution.com created pull request 'Put title box in PDF export Schematics/Fireball_VCO.pdf | Bin 0 -> 86371 bytes rename LUTHERS_VCO.diy => Schematics/LUTHERS_VCO.diy | 0 3D Printing/Rails/18hp_innie.stl create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/DIP-6_W7.62mm_Socket_LongPads.kicad_mod delete mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/C_Rect_L7.2mm_W7.2mm_P5.00mm_FKS2_FKP2_MKS2_MKP2.kicad_mod delete mode 100644 3D Printing/Panels/BLADE BARRIER.png | Bin 16369 -> 0 bytes Latest commits for file Schematics/SynthMages.pretty/Perfboard_1x12.kicad_mod # Temporary files *.lck # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes Total unplated holes count 16 Not plated through holes are merged with plated holes count 16 Not plated through holes: unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated.
- -0.295595 0.890412 facet normal -0.0419816 -0.554754 0.830954.
- 1.230855e-04 vertex -9.325429e+01 1.047901e+02.
- Images/captest.png | Bin 0 -> 11930 bytes.
- 0.734384 0.392538 0.55371 facet normal 1.642182e-15 -1.709773e-15 -1.000000e+00.
- Normal 4.323932e-002 7.566883e-002 9.961951e-001 vertex.