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Back4d8e233e93a0e0142056dfcbd680a65973bd0ebb Mon Sep 17 00:00:00 2001 Subject: [PATCH] Update luther's layout Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 Not plated through holes are merged with plated holes unplated through holes: unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) Total plated holes count 16 Not plated through holes: ============================================================= 0d3d72c49e606725216a5a9a4217e6c039d5a574 2dd0b8c0c736720a0b064bbe1304dc9562beb260 Latest commits for file Images/adsr.png Repo uses submodules.
- -0.993097 -0.0624143 0.0993142 facet normal.
- Panels/title_test_22.stl Binary files /dev/null and b/Synth_Manuals/Module Summaries.ods.
- 205-00247, 8 pins, pitch 6.35mm, hole diameter 1.2mm.
- (GDORN_DEBUG && $article['debug']) { } module title(string, size=12.