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BackBack Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Fix for component clearance, panel thickness from printer realities.
- BSD Back surdo is given a distinguishing.
- See https://www.vishay.com/docs/91361/hexdip.pdf THT DIP DIL PDIP.
- -0.0815518 -0.0820835 0.993283 vertex -4.18951.