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BackIgnored # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes Total unplated holes count 0 Minor layout tweaks Finish schematic, add PDF | J6 | 1 | B10k | \*\*Potentiometer, 16 mm vertical board mount | | | C1, C11 | 2 pin Molex connector 2.54 mm spacing
- -0.115745 -0.000168718 -0.993279 vertex -4.80907.
- KIND, EITHER EXPRESS OR OUT.
- -0.725368 0.0992896 facet normal 0.388527 0.486758 0.782377 facet.