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Https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=95, NSMD pad definition Appendix A BGA 324 0.8 GateMate FPGA Maxim WLP-12, W121H2+1, 2.008x1.608mm, 12 Ball, 4x3 Layout, 0.4mm Pitch, https://www.ti.com/lit/gpn/ina234 Texas Instruments, DSBGA, area grid, YBG pad definition, 0.704x1.054mm, 6 Ball, 2x3 Layout, 0.5mm Pitch, https://www.st.com/resource/en/datasheet/stm32wl54jc.pdf ST UFBGA-121, 6.0x6.0mm, 121 Ball, 11x11 Layout, 0.5mm Pitch, 0.3mm.

• 0 19.4867 vertex 2.6794 1.7206.
• 53c46eece1 Still trying to implement chaining Add.

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