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BackSimulations/*.raw Simulations/*.txt Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole Total plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) Total plated holes count 16 ============================================================= Total unplated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file View File sr1_full.png Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/Push_button_A-5050.kicad_mod Normal file Unescape Hardware/Panel/precadsr_panel_al/precadsr_panel_al.sch Normal file Unescape Hardware/Panel/precadsr_panel_al/precadsr_panel_al.kicad_pcb Normal file Unescape Schematics/Enlarge/Enlarge.kicad_sch Normal file View File Panels/label_test.stl Normal file Unescape Schematics/SynthMages.pretty/Perfboard_1x12.kicad_mod Normal file View File Images/PXL_20210831_004139245.jpg Normal file Unescape.
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