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Back=> Panels/Futura Heavy BT.ttf => Panels/Futura Heavy BT.ttf | Bin 0 -> 16561 bytes create mode 100644 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-PasteTop.gtp create mode 100644 Hardware/Panel/precadsr_panel_al/precadsr_panel_al.sch deleted file mode 160000 Hardware/lib/aoKicad create mode 100644 Hardware/Panel/precadsr_panel_al/precadsr_panel_al.pro delete mode 100644 3D Printing/Pot_Knobs/potentiometre_v3_1.5_merged.stl Normal file Unescape Fireball/Fireball.kicad_pro Normal file View File Hardware/PCB/precadsr_Gerbers/precadsr-B_Mask.gbr Normal file Unescape Hardware/PCB/precadsr_aux_Gerbers/precadsr-F_Cu.gbr Normal file Unescape Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: unplated through holes: ============================================================= 5ff3077e8252367b7eceb0b21b0803904b695d42 77735c00cc3285131373f5cfc61b82eab5963d12 4675f71e05fc19d3608ee6e5061bbe79ae432fb7 c4e1c30b9b Add jlc constraints DRC; replace order number text Add jlc constraints DRC; replace order number text Add jlc constraints DRC; replace order number text Add jlc constraints DRC; replace order number text main MK_VCO/Panels/luther_triangle_vco_ .scad.
- Normal 9.768409e-01 -1.084761e-03 2.139643e-01 vertex -9.051197e+01 1.010241e+02.
- EI30, 2VA, 2x Sec.