Labels Milestones
BackLayer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole Total plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) Total plated holes count 16 Not plated through holes are merged with plated holes unplated through holes: unplated through holes: ============================================================= d9153c70802a10d2fe554f80f1a497b409aac630 d9153c70802a10d2fe554f80f1a497b409aac630 sr1 2bd01a1ff2d30ca3cff647bbf3b80645437cc07c Add schematic, start on PCB Checkpoint after tweaking footprints some more, starting over at 14hp cd18ed43dc Added hard sync input. CV.
- 77A L_CommonMode_Toroid, Vertical series, Radial, pin pitch=5.00mm, .
- Vertex -9.390495e+01 9.260618e+01 1.055000e+01 facet normal 5.086398e-001 1.419821e-003.
- // h_wall(h=4, l=right_rib_x); .
- 0.86616 0.000356438 facet normal 9.966022e-001 8.236541e-002 -0.000000e+000.
- Cross-section. 0 to keep.