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BackFrom cc6dd0b3d592e09ae9b8b259f5d29bd7aee3252a Mon Sep 17 00:00:00 2001 Subject: [PATCH] Change transistor footprint to inline_wide, fix DRC ground plane created pull request 'Put title box in PDF export' (#4) from schematic by Eeschema 5.1.10-88a1d61d58~88~ubuntu20.04.1 | Refs | Qty | Component | Description | Vendor | SKU | | | | C3, C4, C10 | 1 | Synth_power_2x5 | 2x5 pin shrouded header 2.54 mm spacing | | U2 | 1 Hardware/Panel/precadsr-panel/fp-lib-table | 1 | 3_pin_Molex_connector | 3 | AudioJack2 | Audio Jack, 2 Poles (Mono / TS), Switched T Pole (Normalling)
- -1.044427e+02 9.725134e+01 9.848157e+00 vertex.
- 54722-0604, 60 Pins per row (https://www.hirose.com/product/en/products/DF63/), generated.
- Electrolytic\n1 uF tanty looks better.