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-0.097633 0.989318 0.108249 facet normal 9.835916e-001 1.804095e-001 -0.000000e+000 vertex 3.318426e+000 4.564005e+000 2.496000e+001 vertex 6.918735e-001 -7.088008e+000 9.983999e+000 vertex 5.444320e+000 -1.646057e+000 2.496000e+001 vertex 1.380968e+000 -5.529187e+000 1.747200e+001 facet normal 4.566410e-001 -7.828537e-001 4.226336e-001 vertex -1.632302e+000 4.829942e+000 2.475471e+001 facet normal -0.940722 -0.3318 0.0703606 facet normal 0.277899 0.916108 0.288996 vertex 8.79978 1.75038 4.79464 facet normal 0.980752 -0.195255 -3.95367e-07 vertex -3.425 0 18.1498 facet normal 9.881418e-01 -2.744388e-03 -1.535194e-01 vertex -9.050485e+01 1.010009e+02 1.165510e+01 facet normal 0.5 0.866026 0 facet normal -0.241718 0.796849 0.553718 facet normal 9.369178e-001 4.171484e-003 3.495247e-001 vertex -4.027078e+000 -1.693740e+000 2.480400e+001 facet normal 2.404282e-06 -1.000000e+00 -4.279217e-07 facet normal 4.851191e-001 8.489587e-001 2.095915e-001 facet normal 0.877365 0.466832 0.110898 facet normal -0.0905846 -0.86972 0.485161 facet normal 0.174179 0.420511 0.890411 facet normal 0.000000e+00 -9.486858e-15 1.000000e+00 facet normal 0.773356 -0.633859 -0.0119696 facet normal 2.588516e-001 6.303782e-004 9.659169e-001 facet normal 5.127229e-14 -1.000000e+00 1.556656e-14 facet normal 0.0645475 -0.533422 0.843383 facet normal -2.304122e-004 -4.032215e-004 -9.999999e-001 Latest commits for file Schematics/SynthMages.pretty/C_Rect_L22.0mm_W6.1mm_P20mm_MKT_BIG_RED_CAP.kicad_mod (grid_origin -1.27 106.172 (grid_origin 121.92 119.38 "Notes": "Layer B.Mask" "Notes": "Layer F.Cu" "Notes": "Layers L1/L2" "Notes": "Layer B.Cu" "Notes": "Layer B.Mask" "Notes": "Layer F.Cu" "Notes": "Layers L1/L2" "Notes": "Layer B.Cu" "Notes": "Layer B.SilkS" ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole Total plated holes Total unplated holes count 0 Minor layout tweaks Schematics/Fireball_VCO.pdf | Bin 0 -> 10724 bytes 3D Printing/Rails/36hp_innie.stl create mode 100644 Schematics/SynthMages.pretty/Perfboard_4x12.kicad_mod Binary files /dev/null and b/Images/IMG_6771.JPG differ Binary files /dev/null and b/caixa_sr2.png differ Latest commits for branch bugfix/v1.1 Add position for resistor between coarse and fine pitch, FM level, pulse wave width, and PWM level. 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