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That we want them to match. We could generate CV some other way for now, such as: * https://www.mouser.com/ProductDetail/Bourns/PTL30-15O0-105A2?qs=fV9UsjselOEqdQiKFAm%2Fog%3D%3D (A1M, orange LED, 30mm travel, 15mm shaft https://www.mouser.com/ProductDetail/Bourns/PTL30-15R0-103B1?qs=X8nz4ozed5glbMOCRmYKzw%3D%3D (B10K, red LED, 30mm travel, 15mm shaft) * https://www.mouser.com/ProductDetail/Bourns/PTL30-15R0-103B1?qs=X8nz4ozed5glbMOCRmYKzw%3D%3D (B10K, red LED, 30mm travel, 15mm shaft) * https://www.mouser.com/ProductDetail/Bourns/PTL30-15R0-103B1?qs=X8nz4ozed5glbMOCRmYKzw%3D%3D (B10K, red LED, 30mm travel, 15mm shaft https://www.digikey.com/en/products/detail/bourns-inc/PTL30-15R0-103B1/3781301 (red B10K) and https://www.digikey.com/en/products/detail/bourns-inc/PTL30-15O0-105A2/7314942 (orange A1M * The SPDT toggle switches eea453f1eeea3c7619b9825ab723148f1dab934e Port in fixes from v1.1 Checkpoint after converting most things to SMD 53c46eece1 Still trying to implement chaining Checkpoint before trying to fit two mounting posts into hole_top = out_row_1 + 12 + 60 + 24; hole_top = out_row_1 + 12 + 60 + 24 + 6.75; hole_left = slider_center - 13; // this is good practice, but ho-dang what a mess romps with traces, vias, and net links Schematics/Unseen Servant/fp-info-cache | 1 | Conn_01x02 | SIP socket, 2.54 mm, 1x2 (see [build notes](build.md)) | | | | C10 | 3 | 10uF | Electrolytic capacitor | | | | | | | C3, C4, C10 | 1 | Conn_01x04 | Pin socket, 2.54 mm, 1x2 (see [build notes](build.md | | | R9, R11, R13 | 3 | 10 uF | Polarized capacitor | | | | Tayda | A-4349 | | L1 | 1 | Synth_power_2x5 | 2x5 pin shrouded header 2.54 mm spacing | | | | | Tayda | A-1955 | | J10 | 1 | | | R4, R6, R7, R30, R31 Switch, dual pole double throw, separate symbols | | | | S1 | 1 Consider replacing transistor through-holes with sockets or with a diode matrix.

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