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Back4.473792e+000 2.494118e+001 vertex -1.381005e+000 3.992813e+000 2.494118e+001 facet normal -5.284114e-01 -8.489884e-01 -3.401810e-04 vertex -1.010136e+02 1.051113e+02 2.550000e+00 facet normal 0.416182 0.778621 0.469619 vertex 8.21035 -3.40084 5.07603 facet normal 0.163174 0.820341 -0.548101 facet normal 0.000000e+000 0.000000e+000 1.000000e+000 vertex 4.344010e+000 3.615769e+000 2.496000e+001 vertex 2.928430e+000 -4.890075e+000 9.983999e+000 vertex 8.646397e+000 4.992001e+000 0.000000e+000 facet normal 0.555577 -0.831465 0 facet normal 0.95273 -0.286114 0.102199 facet normal -2.294227e-004 3.933168e-004 -9.999999e-001 facet normal 3.152690e-01 3.399096e-03 9.489963e-01 vertex -1.080949e+02 9.695134e+01 8.963632e+00 vertex -1.080268e+02 9.725134e+01 8.942076e+00 facet normal -4.743276e-01 0.000000e+00 8.803484e-01 vertex -1.050340e+02 9.715134e+01 9.208996e+00 facet normal 0.683044 0.365095 0.63258 facet normal -0.463056 0.0914036 0.881604 facet normal -0.561108 -0.299919 0.771496 facet normal 9.975497e-001 4.442017e-003 6.982002e-002 vertex -4.004743e+000 -5.115412e-002 2.470218e+001 facet normal 0.471435 -0.881901 3.73804e-06 facet normal -2.304122e-004 -4.032215e-004 -9.999999e-001 Latest commits for file Docs/precadsr_layout_front.pdf Panels/dual_vca.scad Normal file View File main precadsr/.gitignore 58 lines # Temporary files *.000 *.bak *.bck *.kicad_pcb-bak *.kicad_sch-bak *-backups */fp-info-cache *.kicad_prl *.sch-bak *~ _autosave-* *.tmp *-save.pro *-save.kicad_pcb fp-info-cache # Autorouter files (exported from Eeschema *.net # Autorouter files (exported from Eeschema *.net # Autorouter files (exported from Eeschema) *.net # Autorouter files (exported from Pcbnew # Exported BOM files *.xml *.csv # KiCad backups folders temp_* # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Update current state of project. Add correct footprints to fireball From e9734fb673e2df8488e62f7bd94252034b048666 Mon Sep 17 00:00:00 2001 Subject.
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