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(see https://www.intersil.com/content/dam/Intersil/documents/l72_/l72.10x10c.pdf LFCSP VQ, 48 pin, exposed pad: 4.5x8.1mm, with thermal vias with large copper area, as proposed in http://www.ti.com/lit/ds/symlink/tps5430.pdf TSOP-I, 24 Pin (https://www.jedec.org/standards-documents/docs/mo-142-d variation EB), generated with kicad-footprint-generator JST PHD series connector, S10B-XASK-1.

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