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BackDate Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 ============================================================= Total unplated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes are merged with plated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file View File main precadsr/Docs/precadsr_bom.md 59 lines Latest commits for file Images/PXL_20210831_002553634.jpg main synth_tools/README.md 0 lines From 4ee68877235c53d350cd6d734e74936e7f605c70 Mon Sep 17 00:00:00 2001 Subject: [PATCH 12/13] Update Schematics/schematic_bugs_v1.md Schematics/schematic_bugs_v1.md | 1 | 100k | Resistor | | | | Tayda | A-3545, A-3489, or A-3499\*\*\* | | D3, D4, D5, D6, D7, D8, D9, D10 | 8 | 1N4148 | 100V 0.15A standard switching diode, DO-35"/>