synth_tools

Back

Normal -0.124726 0.987209 0.0993092 vertex -0.627905 -9.98027 0 facet normal 0.0754488 0.766032 -0.63836 facet normal -7.388658e-01 3.468942e-03 -6.738436e-01 facet normal -0.828696 0.0816193 0.553715 facet normal 1.519548e-001 9.883875e-001 -0.000000e+000 vertex 3.858692e+000 5.902027e+000 9.983999e+000 vertex -7.030236e+000 -6.264523e-001 1.747200e+001 facet normal 0.075425 0.766035 -0.638358 facet normal -0.0546376 -0.554748 0.830223 facet normal -0.24378 -0.297045 0.92322 facet normal -0.904824 -0.425785 0 Latest commits for file Fireball/Fireball_panel.kicad_pro Latest commits for file Envelope/Envelope.kicad_pro Latest commits for file Schematics/SynthMages.pretty/C_Rect_L22.0mm_W6.1mm_P20mm_MKT_BIG_RED_CAP.kicad_mod (grid_origin -1.27 106.172 (grid_origin 121.92 119.38 "Notes": "Layer F.SilkS" "Notes": "Layer F.Mask" "Notes": "Layer F.SilkS" "Notes": "Layer B.Cu" "Notes": "Layer F.Cu" "Notes": "Layers L1/L2" "Notes": "Layer F.Paste" "Notes": "Layer F.Mask" "Notes": "Layer B.Mask" "Notes": "Layer B.Mask" "Notes": "Layer F.SilkS" "Notes": "Layer B.Paste" "Notes": "Layer B.Paste" "Notes": "Layer B.Paste" "Notes": "Layer B.Mask" "Notes": "Layer F.Paste" "Notes": "Layer B.Mask" "Notes": "Layer F.Cu" "Notes": "Layers L1/L2" "Notes": "Layer F.Mask" "Notes": "Layer F.Mask" "Notes": "Layer F.SilkS" "Notes": "Layer F.SilkS" "Notes": "Layer B.Paste" "Notes": "Layer B.Mask" "Notes": "Layer F.Mask" "Notes": "Layer F.Paste" "Notes": "Layer B.Paste" "Notes": "Layer F.Mask" "Notes": "Layer B.Mask" "Notes": "Layer F.Cu" "Notes": "Layers L1/L2" "Notes": "Layer B.SilkS" ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole Total plated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes are merged with plated holes count 16 Not plated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00 2001 Subject: [PATCH] rm al panel Hardware/Panel/precadsr_panel_al/fp-lib-table | 4 .../precadsr_aux_Gerbers/precadsr-NPTH.drl | 4 .../precadsr_Gerbers/precadsr-Edge_Cuts.gbr | 4 From 2476d4512ed88199eab1d31bec7610a192015386 Mon Sep 17 00:00:00 2001 Subject: [PATCH] More cleanup c5e8dbdd1f5bb4b2a027556e63f3cebc1db3a56a More cleanup Schematics/Fireball.kicad_sch | 400 (50 "User.1" user (51 "User.2" user (52 "User.3" user.

New Pull Request

Labels Milestones