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Back# LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole Total plated holes count 16 Not plated through holes are merged with plated holes Total unplated holes count 0 Minor layout tweaks merged pull request 'new_footprints' (#5) from new_footprints into main Merge pull request synth_mages/MK_VCO#1 cfb5bfb128 Finish schematic, add PDF' (#2) from schematic by Eeschema 5.1.10-88a1d61d58~88~ubuntu20.04.1 **Component Count:** 76 | Refs | Qty | Component | Description | Manufacturer | Part | Vendor | SKU | | S1 | 1 | LED | Light emitting diode | | | | | | Tayda | A-1847 | | | | J7 | 1 Hardware/PCB/precadsr/sym-lib-table | 1 | 10nF | Film capacitor | | | | S2 | 1 Hardware/PCB/precadsr/sym-lib-table | 1 delete mode 100644 Hardware/Panel/precadsr-panel/precadsr-panel-rescue.kicad_sym create mode 100644 Hardware/PCB/precadsr/Kosmo_panel.pretty/fastestenv_Panel_Mounting_Hole.kicad_mod create mode 100644 Hardware/PCB/precadsr/Kosmo_panel.pretty/Kosmo_Panel_Dual_Mounting_Holes_NPTH.kicad_mod create mode 100755 VCO_MANUAL_v2.pdf