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BackBy 3.16 mm. (8.89 mm vs (10.54+1.52) mm if I'm reading it right. Latest commits for file PSU/PSU.md //clock rate (rv11 // once/continuous (switch // cv out (j7/j6 // pause cv in (j18/j19 // run/stop (sw14 // 1 for manual reset (sw16 // 8 Sockets: // clock out (j5/j12) // glide in (sleeve and normal with extra swing. Caixa and Repique Delete Page Deleting the wiki page "Modules Index" cannot be undone. Continue? 5cacbfea2e Add polygon calculation for wing plates Add VCA shaek layout Add VCA shaek layout Adding SynthMages footprint library Notes from MK's PCB livestream # Format documentation: http://kicad-pcb.org/help/file-formats/ # Temporary files *.000 *.bak *.bck *.zip *.DS_Store *~ .gitignore-extra *.dsn *.kicad_pcb-bak *.kicad_sch-bak *-backups */fp-info-cache *.kicad_prl *.sch-bak *~ _autosave-* *.tmp *-save.pro *-save.kicad_pcb fp-info-cache # Netlist files (exported from Eeschema *.csv *.lck ########################## # Additional ignored # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes count 16 Not plated through holes are merged with plated holes count 0 Minor layout tweaks From 8f3ce8359ba460976b5ffcbe5a92590e33120bbc Mon Sep 17 00:00:00 2001 Subject: [PATCH] Add polygon calculation for wing plates 5cacbfea2e523d618ea3bcbc0bca9c37eb36f10d Update README.md 83b013c3637bfb179ad62b90a6c8b2f5fb547c8c Update README.md README.md | 8 | 1N4148 | 100V 0.15A standard switching diode, DO-35 2x5 pin shrouded header 2.54 mm spacing | Tayda | A-3545, A-3489, or A-3499\*\*\* | | | Tayda | A-1955 | | S3 | 1 | SW_3PDT_x3 | Switch, single pole double throw, separate symbols"/>