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Back(grid_origin -1.27 106.172 (grid_origin 121.92 119.38 "Notes": "Layer B.Paste" "Notes": "Layer F.SilkS" "Notes": "Layer F.Paste" "Notes": "Layer F.Mask" "Notes": "Layer B.Mask" "Notes": "Layer B.Mask" "Notes": "Layer F.SilkS" "Notes": "Layer F.SilkS" "Notes": "Layer F.Cu" "Notes": "Layers L1/L2" "Notes": "Layer F.SilkS" "Notes": "Layer B.Paste" "Notes": "Layer F.Cu" "Notes": "Layers L1/L2" "Notes": "Layer F.Mask" "Notes": "Layer B.Paste" "Notes": "Layer F.Paste" "Notes": "Layer F.Mask" "Notes": "Layer B.Mask" "Notes": "Layer B.Paste" "Notes": "Layer B.Cu" "Notes": "Layer B.Cu" "Notes": "Layer B.Paste" "Notes": "Layer F.Paste" "Notes": "Layer F.Mask" "Notes": "Layer B.SilkS" ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 0 Minor layout tweaks Finish schematic, add PDF Finish schematic, add PDF Finish schematic, add PDF' (#2) from schematic by Eeschema 5.1.10-88a1d61d58~88~ubuntu20.04.1 | Refs | Qty | Component | Description | Vendor | SKU | | | J2 | 1 | Conn_01x02 | SIP socket, 2.54 mm, 1x10 Pin header, 2.54 mm, 1x10 | | R9, R11, R13 | 3 | 1nF | Film capacitor | | C7, C12 | 1 | SW_DPDT_x2 | Switch, single pole double throw, separate symbols
- 28 .../ao_tht.pretty/analogoutput.kicad_mod | 213 .../ao_tht.pretty/analogoutput_12mm.kicad_mod .
- (end 2.691 2.149 (end 2.691 2.149 (end.
- Pitch=5.30mm, , length*width=14*5.6mm^2, Bourns, 5700, http://www.bourns.com/docs/Product-Datasheets/5700_series.pdf L_Toroid Vertical.
- -0.097551 0.990437 0.0975617 facet normal -0.0915932 -0.0112271 0.995733.
- Submodule doc From 13c8bcac477b612d33e1b1cfe89a6f9adc0a8935.