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BackPanels/title_test.stl STLs, 10hp version, others schematics b404e3f9c5 Update luther's layout Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes count 16 Not plated through holes: ============================================================= 4675f71e05fc19d3608ee6e5061bbe79ae432fb7 c4e1c30b9b Add jlc constraints DRC; replace order number text Fireball/Fireball_panel.kicad_pcb | 3 Hardware/Panel/precadsr-panel/fp-lib-table | 4 | 100k | Resistor | | | | | | J5, J12, J13 | 3 | 1nF | Film capacitor | | | | Tayda | A-804 | | | Tayda | A-1135 | | Tayda | A-159 | | J9 | 3 | A1M | **Potentiometer, 9 mm vertical board mount. Only 16 mm vertical board mount | | | | Q1, Q2, Q3 | 3 | A1M | \*\*Potentiometer, 16 mm vertical board mount OR: | | Tayda | A-1605 | | | C1, C11, C12 | 3 | 1k | Resistor | | | | | | D6, D7 | 2 jackHoleDepth = 10; // [1:1:84] //Second row interface placement fm_in .
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