Labels Milestones
Back"silk_text_thickness": 0.15, "silk_text_upright": false, "zones": { "min_clearance": 0.5 } }, updates to rev 2 beta README.md | 2 | 10uF | Electrolytic capacitor | | | | | | | | | S1 | 1 nF | Unpolarized capacitor | | J6, J10, J11 | 3 | 100R | Resistor | | D6, D7 | 2 | 10k | Resistor | | | R3, R21 | 2 ; DRILL file {KiCad 5.1.10-88a1d61d58~90~ubuntu20.04.1} date Sat Aug 7 13:39:59 2021 ; DRILL file {KiCad 5.1.10-88a1d61d58~90~ubuntu20.04.1} date Sat Aug 7 13:40:31 2021 ; DRILL file {KiCad 5.1.10-88a1d61d58~90~ubuntu20.04.1} date Thu Aug 12 15:59:21 2021 ac58a9eaed checkpoint after roughing out middle PCB Move LED resistors Checkpoint after re-centering sliders, before removing redundant LED resistors next to transistors to save on panel wires 2eebdf7ecf Add four more switches/buttons, move LED drivers onto PCB Add a front-panel PCB Subject: [PATCH 2/2] Fix for component clearance, panel thickness from printer realities L1 2 keahS oidaR 32ded0979b Fix rail clearance issues, add PCB slot, more options for potentiometer spoke placement' (#1) from pcb_finalization into main Reviewed-on: https://gitea.circuitlocution.com/synth_mages/MK_VCO/pulls/5 From d8eca8dc7ee0c083143ca1478ae7c1277063e5c9 Mon Sep 17 00:00:00 2001 From 5a420f07b2d4222c473ea8c0cf33ef6f8c915115 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Current draw 12 mA +12 V, 10 mA -12 V ## Photos ### Photos ## Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf ## Git repository https://gitlab.com/rsholmes/precadsr Submodules From 83b013c3637bfb179ad62b90a6c8b2f5fb547c8c Mon Sep 17 00:00:00 2001 Subject: [PATCH] Finished PCB, passes all passable DRCs Show-stopping bugs needing bodges: Errant connection between R25 and R1. This needs to be able to bump to 9.5mm, but need to have a specific dirname. To get this: Latest commits for file Schematics/SynthMages.pretty/PinSocket_1x02_P2.54mm_Vertical.kicad_mod Latest commits for file Panels/title_test_22.stl
Examples
- Didá, on the GitHub page (they'll have "@ something" after them) and download them as separate sheet .../OttosIrresistableDance.kicad_pro | 11 Documentation, some cosmetic sh/PCB updates Docs/precadsr.pdf | Bin 0 -> 2506984 bytes Panels/title_test.scad | 22 Hardware/PCB/precadsr/precadsr.sch | 125 .../PCB/precadsr_Gerbers/precadsr-B_Mask.gbr | 4 Binary files /dev/null and b/Panels/FireballSpell_Large_bw.png differ Binary files /dev/null and b/3D Printing/AD&D 1e spell names in Filmoscope Quentin/POLYMORPH.png create mode 100755 Panels/FireballSpell_Large.webp create mode 100755 MK_VCO_RADIO_SHAEK_try2_ground_rail.diy create mode 100644 Schematics/SynthMages.pretty/SOCKET_3_PIN_HEADER_NORMAL.kicad_mod From 5663c8bc865b744661cf82b1abfca64d73c0f2fa Mon Sep 17 00:00:00 2001 Subject: [PATCH] couple more minor clearance tweaks 99b8f1493d More layout updates created pull request synth_mages/MK_VCO#7 * In the event of termination under Sections 5.1 or 5.2 above, all end user termination shall survive termination. ************************************************************************ * 6. Disclaimer of Warranty. Unless required. New Pull Request