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Play a lot of wiring and increases risk of noise on power rails. Things best left to external modules: - CV-controlled clock. Presumably the CV in controls the clock feature/seq_chaining Checkpoint before trying to add picture 9f9f6acf76 Add notes about UX component wiring Add notes about UX component wiring \* The Dailywell 3PDT and SPDT toggle switches eea453f1eeea3c7619b9825ab723148f1dab934e Port in fixes from v1.1 Checkpoint after converting most things to SMD 55ee65a5e94ad245f04db09ef472959294e7cca0 Still trying to add glide Update 'README.md' From.

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