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Back*~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole Total plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes count 16 Not plated through holes are merged with plated holes count 0 Minor layout tweaks Finish schematic, add PDF Compare 3 commits » 33729ec97f More repo cleanup, adopt github .gitignore file f45c980890 Align panel to integer pseudo-origin, remove testing text, decrease title label font so we don't lose it bd1352a047 Fix annoyance of 2x05 IDC header THT 1x37 1.00mm single row Through hole angled socket strip SMD 2x19 1.27mm double row Through hole angled socket strip, 1x10, 2.54mm pitch, single row Through hole vertical IDC header THT 2x32 2.54mm double row surface-mounted straight pin header, 2x34, 1.00mm pitch, double rows Through hole straight pin header, 2x25, 2.54mm pitch, double rows Surface mounted socket strip SMD 1x12 1.00mm single row style2 pin1 right Through hole angled pin header, 2x14, 2.00mm pitch, single.
- 100 dB at 10 cm, https://www.cuidevices.com/product/resource/pdf/cmt-8504-100-smt-tr.pdf.
- 0.293113 vertex -4.20094 -4.78188.
- 0.963862 0.099246 facet normal -0.98935 0.097375.
- Diameter=10.5mm, Abacron, AISR-01, http://www.abracon.com/Magnetics/radial/AISR-01.pdf.