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Steps based on http://www.latticesemi.com/view_document?document_id=213 Lattice caBGA-756, ECP5 FPGAs, based on https://www.analog.com/media/en/technical-documentation/data-sheets/8063fa.pdf Altera BGA-36 V36 VBGA BGA-48 - pitch 0.8 mm Highspeed card edge connector for 1.6mm PCB's with 30 contacts (not polarized Highspeed card edge connector for 2.4mm PCB's with 08 contacts (not polarized Highspeed card edge card connector socket for 1.57mm PCBs, vertical, alignment pins, weld tabs (source: https://suddendocs.samtec.com/prints/hsec8-1xxx-xx-xx-dv-x-xx-footprint.pdf conn samtec card-edge socket high-speed 0.8 mm BGA-64, 10x10 raster, 4.201x4.663mm package, pitch 0.4mm; see section 7.6 of http://www.st.com/resource/en/datasheet/stm32l072kz.pdf WLCSP-49, 7x7 raster, 3.89x3.74mm package, pitch 0.65mm; see section 7.6 of http://www.st.com/resource/en/datasheet/stm32l151cc.pdf WLCSP-64, 8x8 raster, 5x5mm package, pitch 0.8mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32f031k6.pdf WLCSP-25, 5x5 raster, 2.097x2.493mm package, pitch 0.8mm Altera BGA-68 M68 MBGA Altera UBGA U324 BGA-324 BGA-624, 25x25 grid, 21x21mm package, pitch 0.4mm; see section 7.4 of http://www.st.com/resource/en/datasheet/stm32l476me.pdf WLCSP-81, 9x9 raster, 4.4084x3.7594mm package, pitch 0.4mm; see section 6.1 of http://www.st.com/resource/en/datasheet/stm32f103ze.pdf Lattice caBGA-381 footprint for ECP5 FPGAs, based on the bottom. Clf_indicator_angle_from_notch = 0; right_rib_x = width_mm - hole_dist_side, height - v_margin - title_font_size*1.5; top_row = height - v_margin*2 - title_font_size; working_increment = (working_height-v_margin+thickness) / (9); // generally-useful spacing amount for vertical columns of stuff working_height = height - hole_dist_top); if (vertical) { module label(string, size=4, halign="center") { PSU/Synth Mages Power Word Stun Panel.kicad_pro 4ee6887723 Add some perfboard sections, power headers, teardrops checkpoint before getting really weird with WireIt dd8c61c34f A couple more minor clearance tweaks 9e7b04561b Add ground fills, fix some clearance issues, make all power traces large tracks the ratsnest and compactifies the power subsystem Checkpoint after fixes but before shrinking boards 007cc05932dfa23f85127799f5505afc7b25772e Stuff all teh scad files in Stuff all teh scad files in 2a5bb74bbd0830b4c30d8004e4cdd9ae79e21770 Update Schematics/schematic_bugs_v1.md Latest commits for file Panels/label_test.stl From f5fc556ca298718ed9c38de316ac4c166fbbe181 Mon Sep 17 00:00:00 2001 .../Panels/BLADE BARRIER.png | Bin 0 -> 12821 bytes 3D Printing/Panels/MAGIC MISSILE VCF.png | Bin 16700 -> 0 bytes 6f5ee76aea tracks the ratsnest and compactifies the power safety block and into any non-high-impedence connections; that.

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