downward in KiCad.SPDTPot (9 / 16 mm vertical pots. You can use this, for instance, to duck a VCA level using a gate. Main synth_tools/Schematics/SynthMages.pretty/6.3mm_NPTH_MAXJLCPCB.kicad_mod 24 lines Binary files /dev/null and b/Panels/futura medium bt.ttf Latest commits for branch smt_version Notes about component heights, swapping rotary and toggle switches eea453f1eeea3c7619b9825ab723148f1dab934e Port in fixes from v1.1 Port in fixes from v1.1 SMT updates d952ec97f3d5e1172c33dcefe438ee5d18f8d87d Start of LM13700 version to see why 744b72ef7e0d94fccfae99ec3cb3514981ac4616 Add simplest muscescore example 5ff3077e82 Fix sr2 blue 2cddc4d62d formatting caixa bits c9e81f0cc6 Image of caxia score Image of caxia score 531ebcae92 Add html test version facet normal -0.679089 -0.550857 0.485175 facet normal 0.272864 0.0376334 0.961316 facet normal -0.688666 0.165341 0.705976 facet normal 0.225362 0.544079 0.808201 vertex 3.88332 1.59016 19.1916 facet normal 0.0922853 0.0580967 0.994036 facet normal -0.115448 -0.000364205 0.993313 facet normal -3.794548e-01 -9.252102e-01 3.420165e-04 vertex -1.002975e+02 9.232502e+01 4.255000e+01 facet normal 0.815358 0.435818.