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5a420f07b2d4222c473ea8c0cf33ef6f8c915115 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Add design rules for jlcpcb Add some perfboard sections, power headers, teardrops checkpoint before trying to add picture Schematics/{schematic_bugs_v1.txt => schematic_bugs_v1.md} | 3 | 1 nF | Unpolarized capacitor | | | Tayda | A-004 | | R31 | 1 | B10k | Potentiometer | | D3, D4, D5, D6, D7, D8, D9, D10 | 8 pin connector, https://www.te.com/commerce/DocumentDelivery/DDEController?Action=showdoc&DocId=Customer+Drawing%7F215079%7FY1%7Fpdf%7FEnglish%7FENG_CD_215079_Y1.pdf%7F215079-4 connector TE-Connectivity Micro-MaTch female-on-board top-entry thru-hole 16 pin with exposed pad (http://www.onsemi.com/pub/Collateral/NCP4308-D.PDF WDFN, 12 Pin Placed - Wide, 7.50 mm Body [TQFP] With Exposed Pad Variation BB; (see Linear Technology 05081707_A_DHD16.pdf DH Package; 16-Lead Plastic DFN (5mm x 5mm); (see http://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/lfcspcp/cp-32/CP_32_27.pdf LFCSP, 48 Pin (JEDEC MO-153 Var FD https://www.jedec.org/document_search?search_api_views_fulltext=MO-153), generated with kicad-footprint-generator.

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