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Align it precisely for repeatability b11a8d31874f2e074879a668b4f6eb5f32915bd6 Change transistor footprint to inline_wide, fix DRC ground plane 56529bef3a0c7d0b31cfccd6b6ce971fb35b4e9c Updates from real TL0x4, probably

find the assembly notes - C1: enlarge footprint; a box film cap for 100v is smaller, but not some kind of odd LFO. * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf ## Git repository * [https://github.com/holmesrichards/precadsr](https://github.com/holmesrichards/precadsr) * [https://gitlab.com/rsholmes/precadsr](https://gitlab.com/rsholmes/precadsr This repo uses submodules aoKicad and Kosmo\_panel. To clone: ``` git clone --recurse-submodules git@github.com:holmesrichards/precadsr.git ``` Schematics/Enlarge/Enlarge.kicad_pcb Normal file View File 3D Printing/Rails/36hp_outie.stl | Bin 0 -> 136810 bytes Images/captest.png | Bin 0 -> 193665 bytes Images/precadsr-panel.png | Bin 0 -> 90091 bytes Latest commits for file Schematics/SynthMages.pretty/POT_2_PIN_Header.kicad_mod From 7d48e110137d43d1f6f9100282eff6558c28f26b Mon Sep 17 00:00:00.

• + hardware fits on shaek.
• 3.562743e-001 -6.107879e-001 7.071116e-001 vertex -3.433037e+000 3.842290e+000 2.484855e+001 facet.
• 3.495325e-001 vertex -4.008690e+000 -1.693658e+000 2.475471e+001.

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