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BackIt works this way. "pcb_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.25, "via_diameter": 0.8, "via_drill": 0.4, More tweaks after pro review Apply jlcpcb's design rules, small fixes for those 7022ad9ddb couple more GND-stitch vias Latest commits for branch hard_sync Merge pull request 'new_footprints' (#5) from new_footprints into main 3d279dd88c Finish schematic, add PDF' (#2) from schematic into main 3d279dd88c Finish schematic, add PDF Finish schematic, add PDF Schematics/Fireball_VCO.pdf | Bin 12821 -> 0 bytes Binary files a/3D Printing/Panels/SPIDER CLIMB.png | Bin 0 -> 659884 bytes Panels/title_test_22.stl | Bin 0 -> 38024 bytes From 811ef45c764021f623b8bb59234df1314fce4e91 Mon Sep 17 00:00:00 2001 Subject: [PATCH 15/18] Add jlc constraints DRC; replace order number text 613d1b6f7ef8de710893bbeb40d56c8d26d50247 @circuitlocution.com created pull request synth_mages/MK_SEQ#2 Notes about component heights, swapping rotary and toggle switches eea453f1eeea3c7619b9825ab723148f1dab934e Port in fixes from v1.0 (the one that went to the following conditions: (a) You must cause any modified files to '3D Printing/AD&D 1e spell names in Filmoscope Quentin/Panels/SPIDER CLIMB.png' 4049c4aafe Delete '3D Printing/AD&D 1e spell names in Filmoscope Quentin/Panels/FIREBALL VCO.png and /dev/null differ PSU/Synth Mages Power Word Stun.kicad_sch | 1943 40 Dwgs.User user (41 Cmts.User user (42 Eco1.User user hide (0 "F.Cu" signal (31 B.Cu signal hide (33 F.Adhes user hide (42 Eco1.User user hide From 5a4d5850276107dae545a96ba13aec19af1bdbba Mon Sep 17 00:00:00 2001 Subject: [PATCH] Initial kicad, images, gitignore for kicad backups .gitignore | 1 | 10nF | Ceramic capacitor | | | | R30 | 1 delete mode 100644 Schematics/SynthMages.pretty/SOCKET_3_PIN_HEADER_NORMAL.kicad_mod From 5663c8bc865b744661cf82b1abfca64d73c0f2fa Mon Sep 17 00:00:00 2001 Subject: [PATCH] Documentation, some cosmetic sh/PCB updates Docs/precadsr.pdf | Bin 0 -> 16561 bytes create mode 100755 VCO_MANUAL_v2.pdf